We are developing custom hardware architecture which supports custom ISA (extended from RISC-V) and we want to use TVM and extend it to run deep learning models on our hardware. Can you help me in how to proceed.
Hi @Yashwanth ,
You can take a look at what I presented in Presenting the generation of code for the Gemmini accelerator - microTVM - Apache TVM Discuss (and the associated paper [2212.03034] Integration of a systolic array based hardware accelerator into a DNN operator auto-tuning framework (arxiv.org)), which sounds exactly like your use case.
Thank you for your response. I will go through this.
Hi @fPecc , Could you please tell me where in TVM pull request did you used/added the ISA for producing the Gemmini accelerator RoCC instructions.
Hi @Yashwanth ,
The ISA extension is provided by the Gemmini developers in a header file, using macros to generate the specific instructions. I am just calling this macros in the generated C code.