hi @nizarzaza thanks for posting!
the link you posted is a bit old, unfortunately that work didn’t get upstreamed.
this is something we partially support, but would love to improve upon. the best way to get an idea of what TVM generates for RISC-V would be to use the Zephyr qemu_riscv32
board. You could follow the microTVM with TFLite tutorial, but replace the board name with qemu_riscv32
. I believe you should be able to get something to compile and run this way.
We do want to support RISC-V including some type of vectorized instructions. We don’t currently have SPIKE included in our CI, but would like to add it, and we have a framework that defines a set of API commands (build, flash, connect) which you could leverage to support SPIKE with microTVM.
Right now, TVM doesn’t have any knowledge of such RISC-V vector instructions, so I wouldn’t expect artifacts for RISC-V to be particularly fast. However, it should be possible to define schedules for RISC-V that leverage those instructions. The main challenge we’ve had is identifying which extension we should support.
let me know if this helps!
Andrew