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Cannot execute for GPU a module made from block builder + LegalizeOps + dlight; for matrix multiplication
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1
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141
|
November 18, 2024
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Error while following docs: x = relax.Var("x", R.Tensor((n, 784), "float32")); InternalError: Check failed: (!actual_type.defined()) is false: Expected type PrimExpr but got runtime.PackedFunc
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1
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114
|
November 18, 2024
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Type check error on conv2d_transpose
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2
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139
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November 17, 2024
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AttributeError: 'XGBoostCostModel' object has no attribute 'pool'
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2
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1269
|
November 13, 2024
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Model compilation error
|
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0
|
120
|
November 13, 2024
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Check failed: (::tvm::runtime::IsContiguous(tensor->dl_tensor)) is false: DLManagedTensor must be contiguous.
|
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0
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125
|
November 13, 2024
|
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Model compilation error
|
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0
|
96
|
November 13, 2024
|
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How to bind placeholder tensor?
|
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0
|
118
|
November 13, 2024
|
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InternalError: Check failed:type_code_ == kTVMObjectHandle (2 vs. 8) : expected Object but got float
|
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1
|
679
|
November 12, 2024
|
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Mapping layers names
|
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1
|
202
|
November 12, 2024
|
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Compilers for ML (C4ML) at CGO 2025
|
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0
|
261
|
November 11, 2024
|
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RPC service error trying to program the ZCU104 with the bitstream
|
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2
|
225
|
November 11, 2024
|
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Java Heap Error in VTA Chisel Model
|
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0
|
113
|
November 10, 2024
|
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How to interpret the Argument Shapes of TVM debugger
|
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0
|
105
|
November 10, 2024
|
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Memory verification failed with Relax
|
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6
|
1316
|
November 7, 2024
|
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Can the Relax pass be applied to a relay module?
|
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1
|
148
|
November 7, 2024
|
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[VTA, RPC] Can't upload custom bit file by RPC on ZCU104
|
|
1
|
318
|
November 6, 2024
|
|
Ultra 96v2 RPC failed to test
|
|
1
|
235
|
November 6, 2024
|
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[VTA PYNQ Z2] Error In running RPC Test Program
|
|
2
|
874
|
November 6, 2024
|
|
[SOLVED] Have version requirement for PyTorch or ONNX for Relax Frontend?
|
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1
|
325
|
November 1, 2024
|
|
Building runtime factory for the TVM graph executor Failed
|
|
1
|
151
|
November 1, 2024
|
|
[Relax] How to optimize matrix multiplication in Relax
|
|
4
|
982
|
October 31, 2024
|
|
automatic scheduler component for dynamic shape relax
|
|
0
|
105
|
October 31, 2024
|
|
Does Relax VM support multithread targeting on x86 CPU?
|
|
8
|
347
|
October 30, 2024
|
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[microTVM] how to generate executable code for new hardware?
|
|
1
|
240
|
October 30, 2024
|
|
Does TVM stack have RAMMER-like optimization?
|
|
0
|
105
|
October 30, 2024
|
|
How to create indexable list of tensors
|
|
0
|
106
|
October 29, 2024
|
|
Error when autotune conv2d
|
|
0
|
177
|
October 27, 2024
|
|
TVMError: Do not have a default for tir.Call
|
|
1
|
167
|
October 26, 2024
|
|
CUDA: misaligned address
|
|
2
|
859
|
October 24, 2024
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