[VTA] When can I make VTA bitstream file with HLS blackbox

Questions
#1

Hi @thierry

I’m trying to apply VTA to Bit Fusion which can calculate dynamic bit range using just one core.

Bit Fusion : https://arxiv.org/abs/1712.01507

But when I make Bit Fusion by c code, latency and resource consumption used to be seriously worse than using verilog. So I found HLS Blackbox, which is only available in Vivado HLS 2019.1 or in higher version that cannot generate bitstream files.

If VTA bitstream could be generated by 2019.1 or higher version, IMO there are a lot of advantages for applying VTA to other ASIC DNN architecture because ASIC does not have micro kernel. So I am indeed looking for VTA that can be run in 2019.1 or higher version, and I want to know if there are any plans to make VTA compatible with 2019.1 version.

#2

Hey @Hagoon, thanks for your message. There are some issues in the vivado TCL script when migrating to 2020.1. My colleague @vegaluis has looked into this, and hopefully it should be a matter of days until we can upgrade all of the scripts to rely on the latest version of Vivado. Thanks!

#3

Thank you for your reply.

#4

I am not sure if it works with latest … I’ve worked it out to make a bitstream with 2019.2 which I had installed. As summary (for 2019.2) the DRAM config needs a new parameter. Also .sysdef is gone …

Here is my diff:

--- a/hardware/xilinx/scripts/vivado.tcl
+++ b/hardware/xilinx/scripts/vivado.tcl
@@ -16,15 +16,15 @@
 # under the License.
 
 # Check if script is running in correct Vivado version.
-set scripts_vivado_version 2018.3
-set current_vivado_version [version -short]
-
-if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
-   puts ""
-   catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado \
-    <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado."}
-   return 1
-}
+#set scripts_vivado_version 2018.3
+#set current_vivado_version [version -short]
+#
+#if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+#   puts ""
+#   catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado \
+#    <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado."}
+#   return 1
+#}
 
 # Parse argument list, derive the clock to utilize
 if { [llength $argv] eq 2 } {
@@ -111,6 +111,7 @@ proc init_fifo_property {fifo width_bytes depth} {
 # Procedure to initialize BRAM
 proc init_bram_property {bram width depth} {
   set_property -dict [ list \
+    CONFIG.use_bram_block {Stand_Alone} \
     CONFIG.Assume_Synchronous_Clk {true} \
     CONFIG.Byte_Size {8} \
     CONFIG.Enable_32bit_Address {true} \
@@ -427,9 +428,14 @@ wait_on_run impl_1
 
 # Export hardware description file and bitstream files to export/ dir
 if {[file exist $proj_path/$proj_name.runs/impl_1/${proj_name}_wrapper.bit]} {
+
+  write_hw_platform -fixed -unified -include_bit $proj_path/$proj_name.runs/impl_1/${proj_name}.xsa
+
   file mkdir $proj_path/export
-  file copy -force $proj_path/$proj_name.runs/impl_1/${proj_name}_wrapper.sysdef \
-    $proj_path/export/vta.hdf
+  #file copy -force $proj_path/$proj_name.runs/impl_1/${proj_name}_wrapper.sysdef \
+  #  $proj_path/export/vta.hdf
+  file copy -force $proj_path/$proj_name.runs/impl_1/${proj_name}.xsa \
+    $proj_path/export/vta.xsa
   file copy -force $proj_path/$proj_name.runs/impl_1/${proj_name}_wrapper.bit \
     $proj_path/export/vta.bit
 }

I don’t know exactly where .sysdef is used and/or the flow needs other updates (systef -> xsa). I’ve tried to look but did not spend a lot of time since it worked as is :wink:

The bitstream is done and it seems to be functional.

Hope this helps,

Mihai

#5

The solution you showed worked!

Thank you sooo much! I was looking for the solution for a long time.

I really appreciate it.