Hi, I am trying to implement and use the VTA on my Ultrascale+ FPGA.
What I’ve done so far is:
- Importing tva.cc, tva.hh, hw_spec.h and hw_spec_const.h in Vitis HLS
- Exporting as IP the four modules fetch, load, compute and store
- Importing them in Vivado and connected them using queues and BRAM Controllers (I based my work on the vivado.tcl script I found in the github repository)
- Cretaed a baremetal vitis project to try to interface with the VTA and see if it works. In particular, I extracted parts of the metal_test source code available in the github repository, my test code is here.
The test fails all the computations. What am I doing wrong here? Thanks!