Hi there.
It’s been quite a while I have worked on it, I will tell you based on what I remember.
Since VTA is made using HLS, I have looked at how HLS translates the VTA and makes those Verilog files.
Using that information, I have put debug flags on that Verilog file synthesized by HLS.
Since the Pynq-Z1 had so limited resources, I have ported into ZCU104 to do so.