[VTA][Pynq][Chisel] Creating bitstream from Chisel source for Pynq-Z2

chaoranli20 · October 11, 2022, 12:12pm

Hello,

Here said VTA from Chisel source cannot support the end-to-end inference of ResNet18 in 2019, is it fixed now for PYNQ Z2?

Thanks

vegaluis · October 11, 2022, 4:09pm

Could you elaborate a little bit more on that?

The chisel version seems to be working alright, I have ported small unit tests that you can try on a cloud FPGA

Let me know if you would like to try it out.

chaoranli20 · October 20, 2022, 9:25am

Thank you for your reply!

I get the Verilog file by running make verilog under chisel code, and use Vivado 2020.1 to generate the bitstream for Pynq z2. Below is the diagram.

The classification tutorial can not work using the former bitstream, but it works well on the bitstream generated following the hls tutorial.

Below, the left picture is the instructions using Chisel bitstream, and the right picture is the instructions using HLS bitstream.

And below are the outputs on the host using Chisel bitstream.

Exception has occurred: TVMError
Traceback (most recent call last):
  4: TVMFuncCall
  3: _ZNSt17_Function_handlerIFvN3tvm7runtime7TVMArgsEPNS1_11TVMR
  2: tvm::runtime::RPCWrappedFunc::operator()(tvm::runtime::TVMArgs, tvm::runtime::TVMRetValue*) const
  1: tvm::runtime::RPCClientSession::CallFunc(void*, TVMValue const*, int const*, int, std::function<void (tvm::runtime::TVMArgs)> const&)
  0: tvm::runtime::RPCEndpoint::CallFunc(void*, TVMValue const*, int const*, int, std::function<void (tvm::runtime::TVMArgs)>)
  File "/home/superran/software/tvm/tvm/src/runtime/rpc/rpc_endpoint.cc", line 801
TVMError: 
---------------------------------------------------------------
An error occurred during the execution of TVM.
For more information, please see: https://tvm.apache.org/docs/errors.html
---------------------------------------------------------------
  Check failed: (code == RPCCode::kReturn) is false: code=kShutdown
  File "/home/superran/software/tvm/tvm/python/tvm/_ffi/_ctypes/packed_func.py", line 237, in __call__
    raise get_last_ffi_error()
  File "/home/superran/software/tvm/tvm/python/tvm/contrib/graph_executor.py", line 207, in run
    self._run()
  File "/home/superran/code/ToGraduate/paper-backend/demo/quantize_pytorch.py", line 121, in <module>
    m.run()

I tried two changes in Chisel code, but the results were the same.

I find the LOG_UOP_BUFF_SIZE in pynq_sample.json is 15, which corresponds to 32KB, while the uopMemDepth in chisel config is 2048, which corresponds to 8KB, so I change uopMemDepth to 8192.
When the clock frequency is 100MHZ, the implementation report is

WNS:~-5
TNS:~-10000
LUT:37368
FF:8778
BRAM:124
DSP:0

I guess the error above comes from the timing problem, so I change the clock frequency to 1MHZ, and the timing problem no longer arises, but the error above remains.

So how can I try to solve the problem?

Thank you!

vegaluis · October 20, 2022, 3:19pm

What about using the DefaultPynqConfig instead of DefaultDe10Config in here?

github.com

apache/tvm-vta/blob/main/hardware/chisel/Makefile#L35


		ifeq (, $(wildcard /usr/share/verilator/include/*))
			$(error "Verilator include directory is not set properly")
		else
			VERILATOR_INC_DIR := /usr/share/verilator/include
		endif
	else
			VERILATOR_INC_DIR := /usr/local/share/verilator/include
	endif
endif


CONFIG = DefaultDe10Config
TOP = VTA
TOP_TEST = Test
BUILD_NAME = build
# Set USE_TRACE = 1 to generate a trace during simulation.
USE_TRACE = 0
# With USE_TRACE = 1, default trace format is VCD.
# Set USE_TRACE_FST = 1 to use the FST format.
# Note that although FST is around two orders of magnitude smaller than VCD
# it is also currently much slower to produce (verilator limitation). But if
# you are low on disk space it may be your only option.

These are the available configurations

github.com

apache/tvm-vta/blob/main/hardware/chisel/src/main/scala/vta/Configs.scala

/*
 * Licensed to the Apache Software Foundation (ASF) under one
 * or more contributor license agreements.  See the NOTICE file
 * distributed with this work for additional information
 * regarding copyright ownership.  The ASF licenses this file
 * to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance
 * with the License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing,
 * software distributed under the License is distributed on an
 * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
 * KIND, either express or implied.  See the License for the
 * specific language governing permissions and limitations
 * under the License.
 */

package vta

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chaoranli20 · October 20, 2022, 3:37pm

Thank you for your reply.

I have set CONFIG=DefaultPynqConfig before running make verilog, and the above error occurred.

vegaluis · October 20, 2022, 3:56pm

Sure, thing.

Does the instruction field changes with the depth of the uop memory as well?

github.com

apache/tvm-vta/blob/main/hardware/chisel/src/main/scala/core/Decode.scala#L72-L73


val uop_end = UInt(C_UOP_END_BITS.W)
val uop_begin = UInt(C_UOP_BGN_BITS.W)

chaoranli20 · October 21, 2022, 2:24am

The instruction field wasn’t changed.

The LOG_UOP_BUFF_SIZE in tvm_root/3rdpatry/vta-hw/config/vta_config.json of both host and pynq is 15, which means the UOP buffer size is 32KB, and the width of UOP is 4B, so I changed the depth of the uop memory to 8K. This is consistent with the following settings.

val C_UOP_BGN_BITS = 13
val C_UOP_END_BITS = 14

Is there any mistake in the above thoughts？

By the way, the above error remains when the width of UOP is 2048, which is the original setting in Chisel VTA.

Thanks.

chaoranli20 · December 9, 2022, 4:33am

Hello, thank you for your reply.

I generated bitstream from Chisel source for pynq under 100 MHz successfully but failed under 10MHz. So why HLS-based Custom VTA Bitstream Compilation for Pynq said

The Pynq board supports 100, 142, 167 and 200MHz clocks.

The Pynq-z2 board is Zynq board, I didn’t find the above words in pynq manual, so why is it mentioned here? Can pynq run at other frequencies？

Thanks.