Hi,
I’m trying to run the demo flow by using the VTA RTL code in the hardware simulator.
After configuring some registers and starting the flow, the fetch module fetches the instructions from the DDR and puts the instructions into the queues between the fetch module and other modules, such as load or computer modules.
However, only 20 instructions are put into the queues due the full of the queues. The load and computer modules don’t read the instructions from the queues.
I’m trying to debug this issue by dump the waveform and found that the flow hangs.
Anyone also encountered this issue?
Thanks