VTA, Chisel: VCR address map

Hi everyone,

I’ve been working on getting VTA up and running on a new target (for now in simulation). I managed to get pretty far along where I have signs of live of the tvm-vta tests poking at the registers in the Chisel-generated RTL. But what currently looks off, are the addresses I get for the register accesses on the AXI-lite io_host interface. I started out with the same spacing as for other targets in vta_config.py where registers for different blocks are spread out by 0x1000. However, this does not seem to match what I get in the RTL chisel generates, where the mux only has addresses in the range of about 0x0-0x3c. I don’t fully understand where those addresses come from in the chisel either…

Is there some additional address translation required here or something? Or do I need to adjust some configuration for the chisel code somewhere?

Thanks in advance, Antoine

Hi @antoinek, I don’t know if this is helpful, but I found a similar issue because the register offsets in pynq_driver.cc did not make sense when generating the Chisel backend. Thanks to this post I noticed that actually, the driver needs to be changed to resemble the de10nano driver.

After doing this I was able to run at least the matrix multiply test without errors on an FPGA

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Hi @fPecc. Thanks for the hint, that was indeed my issue as well. I copied from the pynq driver as I was assuming that should be the most mature one. :slight_smile: But you are completely right, the de10nano driver indeed uses a different register layout that seems to actually match the verilog the Chisel code generates!

Thanks for the help!

Antoine

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