Hi everyone,
I’ve been working on getting VTA up and running on a new target (for now in simulation). I managed to get pretty far along where I have signs of live of the tvm-vta tests poking at the registers in the Chisel-generated RTL. But what currently looks off, are the addresses I get for the register accesses on the AXI-lite io_host
interface. I started out with the same spacing as for other targets in vta_config.py
where registers for different blocks are spread out by 0x1000
. However, this does not seem to match what I get in the RTL chisel generates, where the mux only has addresses in the range of about 0x0-0x3c
. I don’t fully understand where those addresses come from in the chisel either…
Is there some additional address translation required here or something? Or do I need to adjust some configuration for the chisel code somewhere?
Thanks in advance, Antoine