The process of accelerator start is like this:
- Generate instructions on the cpu side, and the instructions are saved on the dram;
- Copy the instructions to the ddr, which is accessible by the FPGA pl, and the memory is managed by the cma library that comes with the xilinx pynq platform;
- The pl device accesses the instructions through the axi interface.
Now the problem is in step 2, the instruction is copied to the ddr, pl access to the data are all 0. We did two things to locate it:
- After the dram is copied to ddr, delay for one minute before letting the pl access the data, at this point the pl is able to fetch the correct data.
- Immediately after the dram copy instruction to ddr, copy the data in ddr to new dram again and print it, the result is correct. The result is correct, which means the copy is effective.
The problem now is that without adding a long delay, the pl side doesn’t get the correct instructions.
Hardware：zcu104
The changes we made were upgrading the vivado version to 2022 and using the pynq img version zcu104_pynq_3.0
Do you have any suggestions? Thank you very much. @ thierry