I am working with a research group that is developing a new hardware accelerator. This new hardware is connected to a Xlinix FPGA, but in order for them to work together, we need the model code to be compiled to Verilog.
My understanding is that TVM currently supports 1. Generating code in C and 2. FPGA (such as Xlinix), but generates directly to bitstream, which skips Verilog altogether.
Is there a way to generate Verilog? If not, how might I go about developing that functionality? Any advice or direction would be greatly appreciated.