TVM Monthly - June 2024

Announcement
#1

As discussed by the TVM PMC, our goal is to provide a monthly summary of the project so users and developers can get a better understanding of the goings on of the TVM community.

Feedback and suggestions are welcomed so that we can further improve these updates.

Community

  • None

RFCs

  • None

We continue to improve Relax, TIR, Frontend and other Runtimes.

AOT

  • #17077 - Correctly calculate workspace for vector types

Arith

  • #17046 - [SVE] Add rewrite rules for indices split by scalable expressions

BugFix

  • #17096 - Update FAttrsGetter to return Map<String, ObjectRef>

  • #17078 - [NCCL] Release NCCL thread_local resources in destructor

  • #17066 - [MetaSchedule] Fix TensorIntrin ‘dot_4x4_i8i8s32_sdot’ is not registered

CI

  • #17055 - [SME][Test] Add additional conv2d tests for asymmetric parameters

CRT

  • #17097 - [Bugfix]Return error code on error from ModuleGetFunction

Dlight

  • #17112 - [TIR]Enable SimdGroup op for Metal

  • #17082 - Use 16x32 spatial x reduction thread extents in GEMV scheduling

Docs

  • #17015 - [DOC] Update Model Links to Include Commit

Frontend

  • #17014 - [ArgParse] Pass default values to target compiler(#13264)

Metal

Relax

  • #17119 - [Bugfix]Set purity=false for LazySetOutput

  • #17118 - [VM] Improved error messages for mismatched parameter count

  • #17110 - Alloc BYOC workspace with R.builtin.alloc_tensor

  • #17089 - [ONNX] Add support for HardSigmoid

  • #17100 - [KVCache] Unlimited depth blocks

  • #17075 - [Transform] Modify FuseTIR pass to propagate buffer attributes

  • #17088 - [ONNX] Add support for HardSwish

  • #17085 - [PyTorch] Add support for torch.nn.Hardsigmoid

  • #17083 - [TVMScript]Preserve tir.SizeVar through TVMScript round-trip

  • #17086 - Ignore dynamic parameters in RewriteDataflowReshape

  • #17084 - [PyTorch] Add support for torch.nn.Hardswish

  • #17074 - [KVCache][Test] Fix TIR attn kernels for uncommon group size

  • #17067 - Add missing white spaces in error messages

  • #17061 - [Frontend][Onnx] Cast Op special handling for ShapeExpr input

Relay

  • #16983 - [BugFix]skip leaf args when matching ‘path’ part for dominator pattern

Runtime

  • #17057 - Stateless interface of PagedKVCache leaf node commit

TIR

  • #17098 - [RPC] Allow RPC calls to compiled PrimFuncs with no arguments

TOPI

  • #17048 - [SME]Add conv2d NHWC SME fp16->fp32 schedule

TVMScript

  • #17107 - Better Type Annotation for TIR OP

Misc

  • #17113 - [CudaGraph] Handle exceptions thrown while capturing cuda graph

  • #17094 - [Utility][Container] Support non-nullable types in Array::Map

  • #17101 - [RPC] Raise error if server process terminated

  • #17092 - [UnitTests] Use tvm.ir.assert_structural_equal whenever possible

  • #17054 - [SME] Utilize predication in fp32 matmul and conv2d schedules

  • #17079 - [CMake] Show NVCC include directories in compile_commands.json

  • #17076 - [SME] Extract gemm block correctly when fused with bias

  • #17071 - [WebGPU] Translate int8x4 into u32

  • #17065 - [FP8][Codegen] Add make_fp8 vector constructors

  • #17064 - Add docs of v0.15.0 and v0.16.0

  • #16985 - [CODEGEN] Vector-Codegen support for llvm-pure-intrin

  • #17058 - Introduce outer reduction for metal

  • #17051 - Use adapter.info when available instead of requestAdapterInfo

1 Like