Hi,
I was trying to compile a U-Net style model after applying a layout conversion pass from NCHW to NHWC but got this error while building. The model is from a pre-trained ONNX model.
I’ve noticed that this error only occurs when I use opt_level=3 for the pass that converts the layout. Builds fine with opt_level=2.
I’ve tried this on both a CUDA and Apple Metal (M1 Air) backend and got the same error. Am I missing something?
tvm-bug-recreate - Google Drive [Drive Link] to the Python3 script, shell output of the schedule that was problematic, and the ONNX model.