Line 286: 3082 Killed "$RDI_PROG" "$@"

When I generate bitstream with Xilinx Toolchains, I meet a trouble. After

make ip MODE=sim

It seems synthesis successfully. When I

make

it , there is an error.

wait_on_run impl_1
[Thu Mar  4 00:36:41 2021] Waiting for impl_1 to finish...
/home/k/vivado/Vivado/2020.1/bin/loader: line 286:  3082 Killed                  "$RDI_PROG" "$@"
Makefile:68: recipe for target '/home/k/tvm/3rdparty/vta-hw/hardware/xilinx/../../build/hardware/xilinx/vivado/sim_1x16_i8w8a32_15_15_18_17/export/sim_1x16_i8w8a32_15_15_18_17.bit' failed
make: *** [/home/k/tvm/3rdparty/vta-hw/hardware/xilinx/../../build/hardware/xilinx/vivado/sim_1x16_i8w8a32_15_15_18_17/export/sim_1x16_i8w8a32_15_15_18_17.bit] Error 137

What’s wrong with it? Is it a problem that my main memory(16G) is not enough?

k@ubuntu:~/tvm/3rdparty/vta-hw/hardware/xilinx$ df -h

Filesystem Size Used Avail Use% Mounted on

udev 3.9G 0 3.9G 0% /dev

tmpfs 796M 9.3M 787M 2% /run

/dev/sda1 144G 79G 60G 57% /

tmpfs 3.9G 320K 3.9G 1% /dev/shm

tmpfs 5.0M 4.0K 5.0M 1% /run/lock

tmpfs 3.9G 0 3.9G 0% /sys/fs/cgroup

tmpfs 796M 48K 796M 1% /run/user/1000

I have met the same problem. Have you solved it?

Yes. I seems you don’t have enough RAM. You can solve it by adding swap.