Huge PR affecting Buffer access semantics landed

Today we merged the PR https://github.com/apache/tvm/pull/9727 which added layout transform as a TE schedule primitive. The PR also includes a change in how buffers are loaded / stored, resulting in the massive change throughout the codebase. If you are working on something that touches TIR, you probably need to rebase and resolve conflicts.

Ideally, we would break the PR into smaller ones and land each of them step-by-step. But due to various reasons, we decided to land the PR wholesale. More details and follow-up actions are described in https://github.com/apache/tvm/issues/10505.

In principle, we do not expect perf regression from this PR. But since the PR added many modifications to the TIR -> ... -> TIR -> codegen pipeline, I wouldn’t be surprised if the lowered output becomes different after this PR. Please report any regression you encounter here.

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Thanks for the announcement and the heads up :+1: :slight_smile:.

@masahi: It really caught us by surprise :scream:. Is there a way to place announcements like this (with the potential of causing additional workload) in a more prominent place?

CC: @SebastianBoblestETAS @UlrikHjort @aca88 @sezgin1947 @cgerum @paulpb

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Ok @MJKlaiber, I think I “pinned” this topic globally, so whenever you visit https://discuss.tvm.apache.org/ you will see this announcement kept at the top. Is this “visible enough”? Or do you also want to see a pinned issue on github?

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looks good! Thanks @masahi :+1: :+1: :+1:

Are there any counterpart in the new fashion for Load/Store 's access predicate?

I don’t find it… cc @Lunderberg @vinx13

Well…predicated load/store could be important on certain hardwares, for example, in CUTLASS

we can consider adding predicates to BufferLoad/BufferStore if needed

@wrongtest one way to quickly work around this issue is to use an intrinsic to represent predicated Load/Store. Alternatively, as @vinx13 mentioned, we might want to bring the predicate back somehow, but it might require a short RFC