I basically want to write a script that sweeps through some configurable values for VTA (I was imagining batch and block size), but I’m a little confused as to how these changes show up. As I understand it, there are two models for VTA, both of which can produce a verilog output:
- The HLS module, which is created by running make in the tvm root directory
- The Scala module, which can be configured directly in Configs.scala, and then turned into verilog by running sbt
For the first way (hls): The documentation I’ve read so far says I should configure the design by editing vta_config.json, but it then says I have to remake all of tvm, which takes a long time, especially if I want to sweep through values. I’ve also been hunting through the makefiles and can’t find the actual process that reads the values produced by vta_config.json. The closest thing I find is in the /vta-hw/hardware/intelfocl Makefile, which writes the bitstream with aoc, which is totally unrelated to the simulation/model process. What are the actual files that are changed by vta_config.json?
For the second way (chisel): The /vta-hw/hardware/intel Makefile seems to read vta_config to get the device name, etc. when it makes the chisel files but not any of the actual values for the size parameters. The documentation says Configs.scala is customizable, so I assume we edit that instead if we want to change the scala values, and then don’t have to remake tvm if the target stays the same. What are the parameters in configs.scala that correspond to the parameters that you can vary in vta_config.json?