Hi , i have a question regarding memory management/planning in tvm .
Lets say we have a hardware architechture with 3 different levels of memory , and we need inputs to sit in
different memory levels of the hardware.
From my current understanding , TVM support 1D DRAM (one of the mem level) accesses for memory accessing and same is reflected in schedules.
I would like to understand if it is possible to somehow inform TVM that a particular input or buffer is sitting in a specific memory level , hence can be reflected in TVM schedules. That is appropriate mem transfers instructions and memory addressing logic.
Any help would be highly appreciated.
a kind cc @tqchen @masahi @sanirudh @areusch for their valuable insights.
IIUC, you’re looking for memory scopes to specify different memory types and cache_read and cache_write schedule primitives to move data between different memory types.
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@sanirudh thanks for the reply , i will go through them and revert back in case of any further questions.
Thank you again for the pointer.
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