Can the TVM stack target RISC-V?

Questions
#1

Hello, I’ve seen a few posts talking about RISC-V support, but it’s not clear to me what the current state is. Could anybody clarify to what extent RISC-V is supported? Could you provide some pointers to repositories or documentation?

Thank you very much!

#2

I’m not quite clear about the extent, but I think the PR Add µTVM Zephyr support + QEMU regression test #6603 should be helpful for evaluating uTVM on RISC-V.

#3

hi @davide-giri,

there’s been some work (see below) to optimize TVM-generated code on RISC-V. at main today, there isn’t anything specific to RISC-V checked-in, but i’m also not aware of anything that would prevent you from running on RISC-V today. could you provide some more clarification which type of RISC-V chip you’re interested in (i.e. linux/bare metal, bit width, accelerators)?

here are some of the aspects of TVM to consider wrt RISC-V support:

  • code generation: TVM can emit LLVM IR or C source, so you should be able to compile TVM against a version of LLVM that supports RISC-V code generation (and specify -mcpu= and/or mtriple= in the target string), or you can compile generated code externally (see the µTVM compilation flow or using export_library directly with the c target).
  • runtime: there are a couple options here:
    • linux-capable machines can either compile TVM directly and run it with the full Python interpreter (note the compile time may be longer than you’d like). alternatively, you could cross-compile apps/bundle_deploy and run standalone.
    • bare metal machines can try the new Zephyr-based runtime. we’ll release a VM soon that includes dependencies needed to try this against real hardware.
  • optimization: as RISC-V is a new platform to TVM, some work needs to be done to make TVM aware of any ISA-specific optimizations. @yrchen has done some work in this area with the RISC-V P extension.
  • accelerators: i’m not aware of any support for specialized hardware accelerators right now. it should be possible to support these using the BYOC flow.

Andrew

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