BYOC with two targets besides LLVM: Compilation Error!

[tristanqiu]

Hi everyone, our team is trying to implement a BYOC flow with a default ARM cpu and two customized accelerators. We are trying to do the annotation and composite matching in the following:

The basic idea is to do: ACC pattern → ACC op → ASK pattern → ASK op, in which the order I think it makes sense: we want ACC to get more priority than ASK to implement the workload.

However, it shows the following compilation error:

Can BYOC experts help us resolve this issue? Seldom examples were presented for BYOC with more than one target, but I believe TVM support this case, am I correct??

[comaniac]

We should support this case. If not, then there might be something we missed. From the error message I guess we miss handling multiple targets somewhere in MergeCompisite or AnnotateTarget pass.

I could take a look when I got time, but if it’s urgent to you, it would be great if you could dive into these two passes and try to find the issue. You are also welcome to send a PR to fix it

[tristanqiu]

Thanks for your reply, Cody.

We have an alternative solution that put single op annotation also as composite function, which makes the calling like this now:

This approach can build without an error, however, the subgraph might look a little awkward:

Fortunately, if made agreement with hardware codegen, the codegen is still able to parse the format.

Finally, we will still look into the first case and create a PR if fixed.