Vector sign extension

1

Is there a way of sign extending the vector? A motivational example is below.

    def extern_generator(ins, outs):
        """Manually write the IR for the extern function, add pipeline"""
        ib = tvm.ir_builder.create()

        vecA = ins[0].vload(0, "int16x32")
        vecB = ins[1].vload(0, "int16x32")

        A_2i = tvm.call_pure_intrin('int16x16', 'vectorInterleave', vecA)
        // vectorInterleaves gets every other element from the original vector
        B_2i = tvm.call_pure_intrin('int16x16', 'vectorInterleave', vecB)

        // Sign extend A_2i from int16x16 to int32x16 - A_2i_sext
        // Sign extend B_2i from int16x16 to int32x16 - B_2i_sext

        C = A_2i_sext * B_2i_sext