# \[µTVM\] Static Runtime Code Generator

**URL:** <https://discuss.tvm.apache.org/t/tvm-static-runtime-code-generator/8986>\
**Category:** Application\
**Created:** [January 28, 2021, 4:36pm UTC](https://discuss.tvm.apache.org/t/tvm-static-runtime-code-generator/8986 "2021-01-28T16:36:39Z")\
**Posts on this page:** 1\
**Showing post:** 6

<div class="post-metadata">

**Author:** ![areusch](https://discuss.tvm.apache.org/user_avatar/discuss.tvm.apache.org/areusch/32/2118_2.png) [@areusch](https://discuss.tvm.apache.org/u/areusch)\
**Post date:** [January 29, 2021, 5:35pm UTC](https://discuss.tvm.apache.org/t/tvm-static-runtime-code-generator/8986/6 "2021-01-29T17:35:53Z")

</div>

@r.stahl You’re right we do need to address disable\_vectorization with the c codegen. Another challenge with using intrinsics with the C codegen is handling C inline assembly in a portable way. The LLVM codegen is a good starting point to avoid these issues, but I believe you need to build TVM against a custom LLVM right now. I think the [NTHU post](https://discuss.tvm.apache.org/t/rfc-enable-tvm-qnn-on-risc-v-with-subword-simd-computation/7967) may have some more links to information about that as well as P-aware operator schedules which may potentially be useful.

---

_[View the full topic](https://discuss.tvm.apache.org/t/tvm-static-runtime-code-generator/8986)._