There seem to be a few different options for FPGAs in TVM, with varying levels of support. Is this somewhat correct?
TVM+VTA, which is then compiled for a Xilinx device (Pynq?) using the Vivado HLS tool. (Is this the approach used to develop the VLDA example in the VTM TechReport? Also the basis of the question here.)
TVM and the OpenCL backend, which supports Xilinx devices via SDAccel and Intel devices via AOCL (recent addition).
TVM and the Verilog backend, which could technically support a variety of FPGA devices.
I’m curious about which of the above options are most interesting for future FPGA support, or if FPGA support itself is interesting/undergoing active development.
I have some experience with FPGA-specific optimizations at the OpenCL level, particularly for Altera/Intel devices, and interested in seeing if any these optimizations could be applied with TVM.
Hopefully this makes sense, I’m still learning how TVM works internally. Let me know if there is any way I can add more accurate information to the question. Thanks.
Hi Lamb,
This is my first post here. I have no experience about FPGAs. However, as a software engineer who are willing to start something about FPGA I’d like to say any of the about points are interesting to me. I guess in general point 2 seems an easy and straightforward solution since you are using FPGA through OpenCL interface.
I am also new to TVM. I worked on several personal projects that using code generation with JVM, LLVM and NVRTC. I am very happy to know the TVM project here. This link https://docs.tvm.ai/dev/index.html#design-and-developer-guide is a good start point for me after reading the tvm source code randomly for several days.
Hi @lamb! Based on your interests, I recommend trying VTA out - it’s a flexible FPGA-based accelerator design to obtain efficient inference of deep learning workloads.
You can try today running ResNet-18 on VTA (https://docs.tvm.ai/vta/index.html) which is pretty neat, and we’re working around the clock to make the front-end more flexible so we can pass other models/operators. We’re also working on supporting more FPGA dev boards including Ultra-96, ZCU102, Amazon F1, and Intel FPGAs.
The OpenCL backend is work in progress, and works for small and simple example. It’s not at a stage where it can run ResNet models for instance, but in the long term it can be quite powerful.