# Different Low-Level IRs?

**URL:** <https://discuss.tvm.apache.org/t/different-low-level-irs/15581>\
**Category:** Questions\
**Created:** [August 25, 2023, 10:51pm UTC](https://discuss.tvm.apache.org/t/different-low-level-irs/15581 "2023-08-25T22:51:24Z")\
**Posts on this page:** 1\
**Showing post:** 5

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**Author:** ![Necrotos](https://discuss.tvm.apache.org/letter_avatar_proxy/v4/letter/n/f9ae1b/32.png) [@Necrotos](https://discuss.tvm.apache.org/u/Necrotos)\
**Post date:** [August 29, 2023, 1:41pm UTC](https://discuss.tvm.apache.org/t/different-low-level-irs/15581/5 "2023-08-29T13:41:37Z")

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Thank you for the in-depth explanation!

> After TIR based scheduling was introduced, there was the introduction of [Metaschedule](https://discuss.tvm.apache.org/t/rfc-meta-schedule-autotensorir/10120), which was designed to work with TIR based scheduling and blocks, so if you move to TIR based scheduling, this might be the right thing to explore.

Is MetaSchedule something that can be expanded for custom hardware? That is the part that wasn’t clear to me also with regard to AutoSchedule and why I started with AutoTune.

I have one more question regarding TIR: How do you begin writing a schedule? For TE, you can define the computation on an abstract level as a reduction, but I can’t find any intro on how you work with the TIR scheduling. Everything seems to indicate that you have to manually write out the loop nests.

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