CodeGen for RISC-V

Hi, I have been trying to compile some tests present in the TVM already. The thing is that the LLVM target I am using is built for RISC-V only. I am replacing the lines defining target in the tests: e.g. target ='sifive-u54', options=None)

Every time I try to run these tests, it says: LLVM ERROR: CPU 'generic' is not supported. Use generic-rv64

Any suggestion or guidance would be appreciated.