Co-simulate TVM/VTA with SystemC

aywkwok · March 15, 2021, 4:36pm

I understand TVM/VTA can co-simulate with Verilog using Verilator according to RFC in:

github.com/apache/tvm

[Hardware][Verilator] Integrating and simulating hardware accelerators in TVM

main ← vegaluisjose:vlator

opened 11:51PM - 24 Nov 20 UTC

vegaluisjose

+346 -0

# Integrating and simulating hardware accelerators in TVM This RFC proposes s…upport for integrating hardware designs in TVM, specifically before they are manufactured in silicon or prototyped in an FPGA. Regardless of the hardware target, ML accelerators are built today using the *waterfall* approach described in the following figure: <img width="400" alt="today" src="https://user-images.githubusercontent.com/2478335/100183190-29b91e00-2e93-11eb-85e7-87af707cc39a.png"> Starting from an accelerator idea, hardware is built incrementally for several weeks or months until it is prototyped. Once this happens, software teams start working on integrating this new piece of hardware to a particular ML framework of choice i.e., TVM. One challenge of this approach is the fact that hardware-design decisions are evaluated too late, which turns out to be counterproductive. Additionally, there are higher probabilities that the target ML model gets updated along the way, which makes the efficiency of this process critical. Motivated by this reality, we believe that ML accelerators should be integrated, and more importantly evaluated once the hardware design process begins. Notably, this approach allows engineers to have design feedback and hardware-software continuous integration from day one, as shown in the following figure: <img width="400" alt="idea" src="https://user-images.githubusercontent.com/2478335/100183212-39d0fd80-2e93-11eb-94bb-a9b31fc4f82c.png"> We achieved this integration by leveraging the fact that most ML accelerators are funnel down to a common hardware language i.e., Verilog, regardless of the source language. Moreover, we have today efficient Verilog-to-C++ open-source compilers i.e., Verilator that can be used to interoperate with Verilog via a simple C interface (CFFI) from TVM. Concretely, this RFC consists on a simple codegen using BYOC, and an *opaque* kernel library, runtime, and device interface that can be implemented by engineers to efficiently integrate ML accelerators with TVM regardless of their design complexity. Also, we provide a small example (demo) that shows how to offload an `add` instruction from a Relay program to a simple hardware implementation (scalar adder) written in Verilog. This example is hosted on a third party repository called `hw-widgets` that we are planning to use for future hardware designs. @tmoreau89 @liangfu @jroesch

What about SystemC? Is it possible to co-simulate TVM/VTA with SystemC? If so, can someone provide guideline how to do it? Thanks.