Any scheduling example code for ASIC/FPGA accelerators?

Questions
1

Is there any example code of explicit memory synchronization to hide memory access latency for ASIC/FPGA accelerators described in Figure 9 of the paper? Do you have any guide or tutorial to implement such a scheduling in TVM layer? Thanks.

2

Dear wonjeon, we are in the process of releasing docs and code examples for hardware accelerators. If you PM me or leave your github ID we can add you as an alpha user to our repo.

Best,

Thierry

3

Sent a PM for my github ID. Please check. Thanks!