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InternalError: Check failed: (!axes.defined() || static_cast<int>(axes.size()) == ndim) is false: Dimension mismatch: axes has 4 elements, but data.ndim = 5
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0
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108
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February 1, 2024
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[Relax] mlc-llm create custom func fail
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0
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97
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January 28, 2024
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What is the usecase for reorder_block_iter_var schedule primitive
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0
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91
|
January 23, 2024
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TVMC tuning for M55/U55 (MPS3-AN547) Arm FPGA Board
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1
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174
|
January 18, 2024
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[TIR] Any Infra to support Block Rasterization?
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0
|
133
|
January 17, 2024
|
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TVMError: LLVM cpu architecture `-mcpu=rocketlake-avx512` is not valid in `-mtriple=x86_64-unknown-linux-gnu`
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0
|
177
|
January 16, 2024
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Tvm target cuda\rocm
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0
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146
|
January 5, 2024
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Does TVM have a visual interface or a place where you can see the optimization process?
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1
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202
|
December 27, 2023
|
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Libdarknet2.0.so is not compatible with arm64
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2
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449
|
December 26, 2023
|
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Flattening a cache_read created buffer
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6
|
272
|
December 11, 2023
|
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[TIR] Register own TIR scheduling primitive
|
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0
|
183
|
December 8, 2023
|
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[TIR] tir schedule compute_at will break the block split steps, its different from te schedule, is that what we expect?
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4
|
235
|
December 8, 2023
|
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MISRA compliance
|
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1
|
221
|
December 5, 2023
|
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[TensorIR] Describing schedulable piece-wise reduce - Affine binding
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3
|
195
|
December 1, 2023
|
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The kernel or script crashed when loading ONNX by tvm
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0
|
263
|
November 30, 2023
|
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Memory Manager: Handling offset param in AllocNDArray
|
|
3
|
191
|
November 28, 2023
|
|
What is the point of annotations in TIR
|
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0
|
231
|
November 23, 2023
|
|
MetaSchedule documentation?
|
|
4
|
525
|
November 17, 2023
|
|
How to get HardwareParams on the pltform
|
|
0
|
138
|
November 9, 2023
|
|
How to set the target when tuning for amd gpus
|
|
0
|
156
|
November 9, 2023
|
|
ExecuTorch in the context of TVM
|
|
1
|
405
|
November 7, 2023
|
|
How can set target with more detail information
|
|
0
|
154
|
November 7, 2023
|
|
"Output must be attached at root" with cache_write
|
|
4
|
223
|
November 6, 2023
|
|
Got error while compiling GPT-2 in tvm
|
|
2
|
358
|
October 31, 2023
|
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[Maybe A Bug] Failed for using vectorize stage
|
|
1
|
529
|
October 27, 2023
|
|
On-the-fly weight validation with TVM
|
|
0
|
213
|
October 25, 2023
|
|
For learning , where to buy Arm(R) Cortex(R)-M55 CPU and Ethos(TM)-U55 NPU
|
|
4
|
945
|
October 25, 2023
|
|
The process of generating c code?
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|
0
|
158
|
October 24, 2023
|
|
Combining/Fusing TensorIR blocks from different primfuncs
|
|
4
|
379
|
October 20, 2023
|
|
What should I do or How to use the c code after I generate it
|
|
0
|
145
|
October 20, 2023
|
